1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device in which bit lines have a hierarchical structure.
2. Description of Related Art
Among semiconductor devices represented by DRAM (Dynamic Random Access Memory), there are devices in which bit lines thereof are hierarchized into local bit lines and global bit lines (see Japanese Patent Application Laid-open Nos. 2000-114491, H11-163292, and H8-87880). The local bit lines are low-order bit lines and are connected to memory cells. Meanwhile, the global bit lines are high-order bit lines and are connected to sense amplifiers. When bit lines are hierarchized, the number of memory cells allocated to one sense amplifier can be increased while shortening a wiring length of local bit lines having a relatively high electric resistance.
FIG. 4 in Japanese Patent Application Laid-open No. 2000-114491 shows a semiconductor device in which sense amplifiers are respectively provided at both ends of a pair of global bit lines, and accessed two memory cells are connected to mutually different sense amplifiers by ON/OFF controlling switches provided in the middle of global bit lines. With this arrangement, data of the two memory cells are simultaneously amplified by the mutually different sense amplifiers, and are simultaneously restored.
FIG. 18 in Japanese Patent Application Laid-open No. H11-163292 shows a semiconductor device, in which bit lines thereof are not hierarchized, but has sense amplifiers respectively provided at both ends of a first bit line that is disconnected in the middle and a second bit line that can be short-circuited via switches. Accessed two memory cells are connected to mutually different sense amplifiers by ON/OFF controlling switches provided in the middle of the second bit line. With this arrangement, data of the two memory cells are simultaneously amplified by the mutually different sense amplifiers, and are sequentially restored.
FIG. 1 in Japanese Patent Application Laid-open No. H8-87880 shows a semiconductor device having a sense amplifier provided at one end of a pair of global bit lines, and accessed two memory cells are amplified by time division. With this arrangement, data of the two memory cells are amplified by the same sense amplifier by time division, and are restored by time division.
However, according to the semiconductor device described in Japanese Patent Application Laid-open No. 2000-114491, because switches are provided in the middle of global bit lines, a parasitic capacitance of the global bit lines increase due to an ON resistance of the switches. Further, because positions of the switches which are turned ON change depending on positions of memory cells to be accessed, a parasitic capacitance connected to one sense amplifier and a parasitic capacitance connected to the other sense amplifier do not necessarily match at a time of a sense operation, and also change at each access. Therefore, an operation margin of the sense amplifier decreases.
According to the semiconductor device described in Japanese Patent Application Laid-open No. H11-163292, because switches are provided in the middle of bit lines, a parasitic capacitance of the bit lines also increases due to an ON resistance of the switches. Further, among the accessed two memory cells, a sense operation and a restore operation are performed simultaneously in one memory cell, but these operations are performed at different timings in the other memory cell. Therefore, a timing margin of control is small.
According to the semiconductor device described in Japanese Patent Application Laid-open No. H8-87880, among the accessed two memory cells, a parasitic capacitance of a global bit line at the time of reading data from one memory cell is different from that of a global bit line at the time of reading data from the other memory cell. Therefore, an operation margin of the sense amplifier decreases. Further, because a restore operation is performed by time division, a potential of a bit line connected to a memory cell to be restored next changes and a restore voltage changes, due to a variation of a potential of a bit line at the time of performing a first restore operation. Furthermore, because restore timings of the two memory cells are different, an apparent information-holding capacity of the memory cell previously restored decreases.